In the field of design of interrupt controllers on mobile chips, an interrupt controller processing mode which is commonly seen at present is a mode of passively receiving an interrupt signal. A structure of a current interrupt controller is as illustrated in FIG. 1. At present, the design of the mobile chip adopts SOC architecture, almost all peripherals are integrated on the chip, different buses and bus bridges are used as slaves to complete interaction with a CPU, and an interrupt line is used as a master to complete interaction with the CPU. All interrupts in peripherals are connected to an interrupt controller by sharing one interrupt line. A sampling interface in the interrupt controller performs sampling to the connected interrupt line and sends a sampling result to an interrupt control logic. When a certain interrupt line connected to the interrupt controller is effective, the interrupt control logic judges whether a current sampled signal is effective according to information preset by a user in a register group through a slave port, such as interrupt enable or not, interrupt triggering mode and interrupt priority. If yes, the sampling interface is controlled to stop performing sampling to the interrupt line of the current response, the interrupt line connected to the CPU is simultaneously enabled to be effective and the CPU is enabled to make a response to the interrupt. The CPU automatically turns off a master interrupt, then operates an interrupt processing program, reads a current corresponding interrupt number from an interrupt controller group, and then processes the corresponding interrupt according to the interrupt number. If a triggering mode of the interrupt to which a response is made is of a level type, an interrupt clear register in the corresponding peripheral further needs to be written in the interrupt processing program to clear an interrupt source. After interrupt processing is completed, the interrupt processing program will write a value required by the interrupt controller into a designated register in the interrupt controller group, and thereby the interrupt control logic will enable the sampling interface to continuously perform sampling to the interrupt line of the current response to make a response to a new interrupt. Simultaneously, the master interrupt of the CPU will be turned on to make a response to other interrupts.
In the abovementioned interrupt processing method of the interrupt controller, for the level-triggered interrupt, under a situation that the interrupt source is not cleared, the interrupt controller will continuously make a response to the current interrupt after making a response to one interrupt, and a system operation fault is caused. Simultaneously, in an SOC system, peripherals are often mounted under sub-buses of different speeds, and when the CPU clears the interrupt source, the CPU needs to access the interrupt clear register of the corresponding peripheral through many bus converter bridges to acquire information needed for clearing the interrupt source; consequently the CPU needs to spent much time in performing an interrupt source clear operation and it is not beneficial to quick response to the interrupt; and the interrupt processing principle is that the time of turning off the master interrupt of the system is as short as possible, and otherwise, the response time of other interrupts will be delayed.